Uvm For Verification Part 3:Register Abstraction Layer (Ral)

Step by Step Guide from Scratch

What you'll learn
Using UVM RAL for verification of DUT Registers and Memories
Understanding different Register as well memories methods
Implementing Frontdoor and Backdoor access methods
Implementing Implicit and Explicit Predictor
Coverage Computation for Register and Memories

Requirements
Basic understanding of Verilog, SystemVerilog, and UVM

Description
Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.The UVM Register layer provides a set of libraries for adopting UVM for verification of DUTs consisting of registers as well as memories. UVM RAL provides a set of abstract methods to access the register as well as memories with either a front-door or back-door access mechanism that are easy to use as well as configurable. We will also be covering the coverage computation we get with UVM RAL. 

Who this course is for:
Engineers involved/interested in the verification of RTL's