Cadence SPB OrCAD 16.60.040 Hotfix
Cadence SPB OrCAD 16.60.040 Hotfix | 1.1 Gb
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 40 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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577694 ALLEGRO_EDITOR OTHER Need to retain padstack edits during "Refresh Symbols"
1105280 FSP MODEL_EDITOR Negative Voltage leads to 'Internal error. Invalid voltage value -12 specified for pin'
1198148 FSP OTHER In the Symbol Setup form instances instantiated multiple times must be customized individually
1200015 CONCEPT_HDL CORE module_order.dat is generated for sym_n view automatically
1275209 PSPICE NETLISTER PSpice is not considering 3K9 as 3.9K if inside a condition in PSpice template
1297335 SPECCTRA FANOUT Wrong fanout created in PCB Editor on using the Route Automatic option.
1316637 CONCEPT_HDL PDF PublishPDF does not set arc lines to the defined line width setting
1320581 ALLEGRO_EDITOR OTHER Dangling line listed in Dangling Line report but no line exists.
1326104 CONCEPT_HDL CORE Pin dots, pin text do not stay on grid in symbol editor on moving/copying.
1329848 CONSTRAINT_MGR CONCEPT_HDL Export Excel from DE-HDL CM displays 'Server busy' message.
1330044 CONSTRAINT_MGR OTHER Need command line equivalent of cmDiffUtility to save reports as HTML
1330122 SIP_LAYOUT PLACEMENT When placing IC type symbols in SiP they are being placed as Wire Bond instead of Flip Chip.
1330930 CONCEPT_HDL CORE Hyperlink in attributes window not working.
1336086 SIP_LAYOUT MANUFACTURING If a design has bondfingers at a certain angle/position the tool does not create a soldermask opening
1338610 MODEL_INTEGRIT TRANSLATION IBIS to DML failed with incorrect error message.
1338925 ALLEGRO_EDITOR MANUFACT Need a 16.5 route file option in SPB 16.6.
1339672 CONCEPT_HDL CORE Editing a symbol in PDV results in error (SPCOCN-1731)
1339987 ALLEGRO_EDITOR SKILL axlFormCreate embeddedForm is not working as expected
1339989 PCB_LIBRARIAN LIBUTIL Con2con exits if Global section of PTF file has NC_PINS
1340342 F2B DESIGNVARI DE-HDL crashes when trying to use Variant commands
1340360 ALLEGRO_EDITOR EDIT_ETCH On running the AiDT command, if Total Etch Length is defined directly on an XNet, PCB Editor crashes.
1340854 CONSTRAINT_MGR CONCEPT_HDL Component properties are lost during backannotation
1341096 SIP_LAYOUT ASSY_RULE_CHECK ADRC rule 'Wire to Pad Optical Short' gives wrong results
1341330 ALLEGRO_EDITOR DRC_CONSTR Spacing rules not followed if bond_pad is set to bond_finger
1342705 ALLEGRO_EDITOR INTERFACES IDX incremental bend areas need delete processed first before adds
1342910 FSP SETTINGS Unable to remove "Don't Use Banks" setting.
1343076 SIG_INTEGRITY OTHER 'OrCAD PCB Professional' tier should not allow Differential Pair extraction
1343239 PCB_LIBRARIAN VERIFICATION Con2con reporting errors against the wrong primitive
1343257 SCM SETUP In SCM, unable to add termination to design.
1343403 CONCEPT_HDL CORE Return code in Search_History prevents DE-HDL launch.
1343749 CONCEPT_HDL CORE Global Navigate does not always respond
1343870 ALLEGRO_EDITOR DATABASE Import Logic changes VIA net names to GND
1343949 FSP IMPORT_ALLEGRO Import Instances from PCB Editor does not import FPGA model
1344265 CONCEPT_HDL CORE DE-HDL crashes on viewing page search
1344413 SIP_LAYOUT DIE_GENERATOR When composing a die From Geometry the die pads are shifting.
1344745 ALLEGRO_EDITOR EXTRACT Need information about the changes in the format of the report generated using axlExtractToFile()
1346277 SIP_LAYOUT DIE_ABSTRACT_IF Shape cannot be read when sip_symed_codesign is set.
1346318 CONSTRAINT_MGR OTHER cmDiffUtility shows "unrelease_unrelease.." message and stops
1346621 ASI_PI GUI Sigrity tools shown in PI Base Analyze menu regardless of option selected
1347103 ALLEGRO_EDITOR INTERFACES Step mapping - 3D view for mechanical symbol
CCRID PRODUCT PRODUCTLEVEL2 TITLE
=================================================================================================
577694 ALLEGRO_EDITOR OTHER Need to retain padstack edits during "Refresh Symbols"
1105280 FSP MODEL_EDITOR Negative Voltage leads to 'Internal error. Invalid voltage value -12 specified for pin'
1198148 FSP OTHER In the Symbol Setup form instances instantiated multiple times must be customized individually
1200015 CONCEPT_HDL CORE module_order.dat is generated for sym_n view automatically
1275209 PSPICE NETLISTER PSpice is not considering 3K9 as 3.9K if inside a condition in PSpice template
1297335 SPECCTRA FANOUT Wrong fanout created in PCB Editor on using the Route Automatic option.
1316637 CONCEPT_HDL PDF PublishPDF does not set arc lines to the defined line width setting
1320581 ALLEGRO_EDITOR OTHER Dangling line listed in Dangling Line report but no line exists.
1326104 CONCEPT_HDL CORE Pin dots, pin text do not stay on grid in symbol editor on moving/copying.
1329848 CONSTRAINT_MGR CONCEPT_HDL Export Excel from DE-HDL CM displays 'Server busy' message.
1330044 CONSTRAINT_MGR OTHER Need command line equivalent of cmDiffUtility to save reports as HTML
1330122 SIP_LAYOUT PLACEMENT When placing IC type symbols in SiP they are being placed as Wire Bond instead of Flip Chip.
1330930 CONCEPT_HDL CORE Hyperlink in attributes window not working.
1336086 SIP_LAYOUT MANUFACTURING If a design has bondfingers at a certain angle/position the tool does not create a soldermask opening
1338610 MODEL_INTEGRIT TRANSLATION IBIS to DML failed with incorrect error message.
1338925 ALLEGRO_EDITOR MANUFACT Need a 16.5 route file option in SPB 16.6.
1339672 CONCEPT_HDL CORE Editing a symbol in PDV results in error (SPCOCN-1731)
1339987 ALLEGRO_EDITOR SKILL axlFormCreate embeddedForm is not working as expected
1339989 PCB_LIBRARIAN LIBUTIL Con2con exits if Global section of PTF file has NC_PINS
1340342 F2B DESIGNVARI DE-HDL crashes when trying to use Variant commands
1340360 ALLEGRO_EDITOR EDIT_ETCH On running the AiDT command, if Total Etch Length is defined directly on an XNet, PCB Editor crashes.
1340854 CONSTRAINT_MGR CONCEPT_HDL Component properties are lost during backannotation
1341096 SIP_LAYOUT ASSY_RULE_CHECK ADRC rule 'Wire to Pad Optical Short' gives wrong results
1341330 ALLEGRO_EDITOR DRC_CONSTR Spacing rules not followed if bond_pad is set to bond_finger
1342705 ALLEGRO_EDITOR INTERFACES IDX incremental bend areas need delete processed first before adds
1342910 FSP SETTINGS Unable to remove "Don't Use Banks" setting.
1343076 SIG_INTEGRITY OTHER 'OrCAD PCB Professional' tier should not allow Differential Pair extraction
1343239 PCB_LIBRARIAN VERIFICATION Con2con reporting errors against the wrong primitive
1343257 SCM SETUP In SCM, unable to add termination to design.
1343403 CONCEPT_HDL CORE Return code in Search_History prevents DE-HDL launch.
1343749 CONCEPT_HDL CORE Global Navigate does not always respond
1343870 ALLEGRO_EDITOR DATABASE Import Logic changes VIA net names to GND
1343949 FSP IMPORT_ALLEGRO Import Instances from PCB Editor does not import FPGA model
1344265 CONCEPT_HDL CORE DE-HDL crashes on viewing page search
1344413 SIP_LAYOUT DIE_GENERATOR When composing a die From Geometry the die pads are shifting.
1344745 ALLEGRO_EDITOR EXTRACT Need information about the changes in the format of the report generated using axlExtractToFile()
1346277 SIP_LAYOUT DIE_ABSTRACT_IF Shape cannot be read when sip_symed_codesign is set.
1346318 CONSTRAINT_MGR OTHER cmDiffUtility shows "unrelease_unrelease.." message and stops
1346621 ASI_PI GUI Sigrity tools shown in PI Base Analyze menu regardless of option selected
1347103 ALLEGRO_EDITOR INTERFACES Step mapping - 3D view for mechanical symbol
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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Name: Cadence SPB OrCAD
Version: (32bit) 16.60.040 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.039
Size: 1.1 Gb
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Cadence SPB OrCAD 16.60.040 Hotfix
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