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CMOS PLL Synthesizers: Analysis and Design by Edgar Sanchez-Sinencio [Repost]
![CMOS PLL Synthesizers: Analysis and Design by Edgar Sanchez-Sinencio [Repost]](https://pixhost.icu/avaxhome/53/ea/0026ea53.jpeg)
CMOS PLL Synthesizers: Analysis and Design (The Springer International Series in Engineering and Computer Science) by Edgar Sanchez-Sinencio
Springer; 2005 edition | January 3, 2005 | English | ISBN: 0387236686 | 232 pages | PDF | 12 MB
Springer; 2005 edition | January 3, 2005 | English | ISBN: 0387236686 | 232 pages | PDF | 12 MB
This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly.